DFPMU - Digital Core Design

ALTERA datasheet
XILINX datasheet
LATTICE datasheet
ASIC datasheet

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Floating Point Coprocessor

The DFPMU is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. The DFPMU directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It does not require any programming, so it also does not require any modifications of the main software. Everything is done automatically during software compi-lation by the DFPMU C driver.
The DFPMU was designed to operate with DCD’s DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered to-gether with the DFPMU package.
The DFPMU uses the specialized CORDIC and standard algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, change sign of a number and trigonometric functions: sine, cosine, tangent and arctangent. It has built-in conversion instructions from integer type to floating point type and vice versa. The input numbers format is according to IEEE-754 standard. The DFPMU supports single precision real numbers, 16-bit and 32-bit integers. The DFPMU is prepared to use with 8-, 16- and 32-bit processors.
The DFPMU is a technology independent design that can be implemented in a variety of process technologies.

Direct replacement for C float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
No programming required
IEEE-754 Single precision real format support – float type
16-bit word and 32-bit short integers format supported – integer types
Flexible arguments and result registers location
Performs the following functions:
- FADD, FSUB – addition, subtraction
- FMUL, FDIV – multiplication, division
- FSQRT – square root
- FCHS, FABS – change of sign, absolute value
- FXAM – examine input data
- FUCOM – comparison
- FSIN, FCOS – sine, cosine
- FTAN – tangent
- FATAN – arctangent
- FILDW, FILD – 16-bit, 32-bit integer to float
- FISTW, FIST – float to 16-bit, 32-bit integer
Exceptions built-in routines
Masks each exception indicator:
- Precision lack PE
- Underflow result UE
- Overflow result OE
- Invalid operand IE
- Division by zero ZE
- Denormal operand DE
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Fast data processing & control

The table and figures below illustrates the system with DFPMU performance improvements for two typical CPU.
The DFPMU floating point instructions performance has been compared to standard C library functions delivered with every commercial C compiler. Each program was executed in the same system environments. Number of clock periods were measured between input data loading into work registers and output result storing after operation. The results are placed in tables below.
Improvement has been computed as a number of clock cycles reuired by the CPU to compute FP operation, by the number of clocks required to compute the same operation by system of CPU with DFPMU:

Device	Improvement
80C51	1.0
DP8051	7.3
DP8051+DFPMU	162.0

IEEE-754 FP Instruction	Improvement
Addition	73
Subtraction	60
Multilication	65
Division	182
Square Root	392
Sine	139
Cosine	144
Tangent	222
Arcs Tangent	182
Average speed improvement:	162

Device	Improvement
CPU	1.0
CPU+DFPMU (arithmetic)	7.5
CPU+DFPMU (trigonometric)	49.2
CPU+DFPMU (overall)	28.3

IEEE-754 FP Instruction	Improvement
Addition	6.4
Subtraction	6.5
Multilication	5.1
Division	6.5
Square Root	12.9
Sine	40.8
Cosine	41.3
Tangent	65
Arcs Tangent	49.6
Average speed improvement:	28.3

clk

rst

datai¹ (31:0)

addr² (4:0)

datao¹ (31:0)

irq

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
datai¹ (31:0)	input	Data bus input
addr² (4:0)	input	Register address to read/write
cs	input	Chip select for read/write
we	input	Data write enable
datao¹ (31:0)	output	Data bus output
irq	output	Interrupt request indicator

Align

Control Unit

Exponent

CORDIC

Interface

datai¹ (31:0)

datao¹ (31:0)

addr² (4:0)

irq

Mantissa

Shifter

clk

rst

Align

It performs the numbers analyze against IEEE-754 standard compliance. Information about the data classes are passed as result to appro-priate internal module.

Control Unit

It manages execution of all instructions and internal operation required to execute particular function.

Exponent

It performs operations on exponent part of number. The addition, subtraction, shifting, comparison and conversion operations are executed in this module. It contains exponents and work registers.

CORDIC

CORDIC performs trigonometric operations on input data. The sine, cosine, tangent and arctangent operations are executed in this module. It contains three work registers.

Interface

It is an interface between external device and DFPAU internal 32-bit modules. It contains data, control and status registers. It can be configured to work with 8-, 16- and 32-bit processors.

^{1 - data bus can be configured as 8-, 16- or 32- bit depends on processor’s bus size}
^{2 - address bus is aligned to work with 8- (3:0), 16- (3:1) or 32- (4:2) bit processors}

Mantissa

It performs operations on mantissa part of number. The addition, subtraction, multiplication, division, square root, comparison and conversion operations are executed in this module. It contains mantissas and work registers.

Shifter

It performs mantissa shifting during normalization, denormalization operations. Information about shifted-out bits are stored for rounding process.

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation	Speed grade	Logic Cells	Frequency [MHz]
APEX20KC	-7	5150	58
STRATIX	-5	4460	108
CYCLONE	-6	4650	90
CYCLONE-II	-6	4520	96
STRATIX-II	-3	3300	168
STRATIX-IV	-2	3900	220

DFPMU implementation results for ALTERA devices. The all features have been included.

Implementation	Speed grade	Slices	Frequency [MHz]
SPARTAN-3	-5	2330	47
SPARTAN-3E	-5	2930	80
SPARTAN-6	-3	1445	80
VIRTEX-II	-5	2330	77
VIRTEX-II pro	-7	2330	85
VIRTEX-4	-11	2930	103
VIRTEX-5	-3	1520	135

DFPMU implementation results for XILINX devices. The all features have been included.

Implementation	Speed grade	LUTs/PFUs	Frequency [MHz]
ispXPGA	-5	5327/1393	42

DFPMU implementation results for LATTICE devices. The all features have been included.

Design	Standard compliance	Arithmetic operations ADD, SUB, MUL, DIV, SQRT, COMP	Trigonometric operations SIN, COS, TAN, ARCTAN	Processors interfaces	Single precision	Double precision	8/16/32 bit integers	52-bit integers
Design	Standard compliance	Arithmetic operations ADD, SUB, MUL, DIV, SQRT, COMP	Trigonometric operations SIN, COS, TAN, ARCTAN	8,16,32 bit	Single precision	Double precision	8/16/32 bit integers	52-bit integers
DFPAU	IEEE-754	+	-	+	+	-	-	-
DFPMU	IEEE-754	+	+	+	+	-	+	-
DFPAU-DP	IEEE-754	+	-	+	+	+	+	+
DFPMU-DP	IEEE-754	+	+	+	+	+	+	+

The main features of each Arithmetic Coprocessors family member has been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.

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