All DCD’s Cores are available as a technology independent HDL Source Code or Netlist for specified FPGA. License is granted for specified number of projects (ASIC, FPGA bit stream) For each Core we have two major license types:

• Single Site License and
• Multi Site License.

Yes, maintenance can be extended to any multiple period of 3 months e.g 6, 9 months.

Yes, the Core price includes a 3 months of maintenance and Core Implementation support. It covers phone & email consulting.

You should first contact with DCD headquarters or DCD representative and choose a Core configuration and License Type you are interested in. Next, You can just sent us a Purchase Order together with signed License Agreement by mail or fax. The Core Package is sent out within 2 business days.

Yes, naturally. Since all DCD’s Cores are available as a technology independent HDL Source Code, they can be fully customized to best meet customer requirements.

You can buy a Netlist License or you can purchase a customized Core without unneeded Core features (peripherals for example).

Yes, all of our Cores are fully tested in hardware and software before public release.

Yes, most of DCD’s Cores have ALTERA AMPP Approved or XILINX AllianceCore Flow Checked stamps. It means that core functionality and performance were tested by particular organizations.

Yes. DCD offers a free evaluation packages, for particular technologies dependent on the customer requirements. During evaluation customer can check if Core meets desired requirements, and if any modification is needed.

Each evaluation license is valid for 30 days by default. You can extend the evaluation period without problems for next 30 days. You should just contact sales@dcd.com.pl and ask for new license file.

DCD doesn’t charge any royalty fees. Each license is one time paid. It simplifies mutual business and makes live easier for both partners.

You can select custom configuration of the core with additional peripherals, DCD do not charge any fees for customization of the core by adding or removing peripherals/features. Total cost of such core is a sum of modules prices.

Typically, evaluation package contains:

• Core as
  • Encrypted ALTERA Megafunction with example project for QUARTUS II tool, or
  • EDIF netlist component for XILINX technolgy, or
  • Compiled HDL Source code into ModelSim library format for ASIC packages
• Core documentation,
• Datasheet,
• Installation note,
• License file

DCD has a lot of world wide customer. Our cores have been implemented in FPGA and ASIC applications. You may check our reference list on-line. For further details please send us an email.

Package is delivered by Express Mail. Delivery to USA usually takes 4 business days. Delivered product package contains:

• CD-ROM with ordered IP Core:
  • Plain text EDIF netlist, VHDL, or VERILOG Source code
  • VHDL, or VERILOG test bench environments:
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
  • Technical documentation:
    • Installation notes
    • HDL core specification
    • Instructions set details
    • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support:
    • IP Core implementation support
    • 3 months of maintenance:
      • Delivery the IP Core updates, minor and major versions changes
      • Delivery the documentation updates
      • Phone & email support
• Printed documentation
  • Installation notes
  • Instructions set details
  • HDL core specification
• License agreement
• Certificate of Authenticity

No, an extra Maintenance is not obligatory. It can be purchased at any time depends on individual customer's needs. Please note that each Licensed Core includes 3 months of Maintenance and Core Implementation support without additional fees.

The following I2C IP Cores are available:

• DI2CM - Master I2C core works in multi-master system with clock synchronization and arbitration features
• DI2CS - Slave I2C controller to use with microcontrollers
• DI2CSB - Base slave I2C controller to use with passive devices such as LCD displays, pressure sensors etc.

Just a clarification of the signal polarity: is the DI2CM SCLHS pin 'high', when the SCL line should be driven 'high'?

Yes, you have right. When SCLHS is high then SCL line should be also driven to logic high. Details are found in DI2CM Core specification.

High speed DI2CM contains one additional pin required to provide 3.4 Mb transmission. There is no need to use special I/O features of particular technology. Standard I/O can be used to provide High Speed transmissions.

One clarification of the high-speed mode driver in DI2CM Core: how are you implementing the 'current-source pull-up' cell? Can this be done by a particular Virtex OBUFT driver, or is external circuits needed?

The OBUFT can be used as current pull-up source. This pull-up is needed to assure "sharp" clock edges when SCL line is loaded by large capacity.

Yes, the evaluation package of each I2C Core is available for any ALTERA device.

Our board has some IIC target chips on the IIC Control chain(mostly from Philips). Was your core tested in this environment? Should I take care about any issue when I place your core with other targets?

Yes, all of our I2C Cores: DI2CSB, DI2CS and DI2CM have been tested on hardware board using Philips I2C chips (PCF8573, PCF8574, PCF8582) for communication purpose. This product is used also by our customers and is fully validated in silicon.

DoCD^TM debug software communicates with Debug IP Core integrated in silicon with uC through Hardware Assisted Debugger (HAD). HAD is a small adapter responsible for communication and data exchange. The HAD supports all major I/O voltage standards:

• 3.3 Volt
• 2.5 Volt
• 1.8 Volt
• 1.5 Volt

• whole DoCD can be turned off after successful debug (when final project is being finalized into an ASIC/FPGA)
• each of 4 hardware breakpoints can be turned off (code execution BP, internal data memory BP, external data memory BP, sfr BP)
• writing data into internal, external memories or SFRs can be turned off
• it works with all DCD's 8051 architectures ( DR8051x, DP8051x, DR80390x, DP80390x)

• Debug IP Core incorporated into microcontroller core
• HAD PCB board (Hardware Assisted Debugger) - used for communication between Debug IP core inside Silicon and Windows Debug Software.
• Windows Debug Software - running on Windows operating systems

Scan test ready means that the IP Core is developed according to all rules needed for automatic insertion of scan test (for example by Synopsys Design Compiler tool). There are certain rules which should be fulfilled by IP Core, to allow automatic testing at pre-production stage of the complete design.

Generally DR8051 can work with most popular 8051 debuggers. However DCD’s has own on-chip debugger called DoCD System (DCD on Chip Debug System). It allows debugging inside hardware (Silicon) and functional simulation of a C/ASM code (Simulator).

DoCD system includes:

• Debug IP Core incorporated into microcontroller core
• HAD PCB board (Hardware Assisted Debugger) - used for communication between Debug IP core inside silicon and Windows Debug Software.
• Windows Debug Software - running on Windows operating systems For more information please see DoCD ^TMsoftware page.