All DCD’s Cores are available as a technology independent HDL Source Code or Plain Text EDIF Netlist.
For each Core we have two major license types:
Single Design License and
Unlimited Designs License.
Can I extend the maintenance over 3 months?
Yes, maintenance can be extended to any multiple period of 3 months e.g 6, 9 months.
Does the core price include maintenance?
Yes, the Core price includes a 3 months of maintenance and Core Implementation support. It covers phone & email consulting.
How to purchase your core?
You should first contact with DCD headquarters or DCD representative and choose a Core configuration and License Type you are interested in. Next, You can just sent us a Purchase Order together with signed License Agreement by mail or fax.
The Core Package is sent out within 2 business days.
Does a core can be modified?
Yes, naturally. Since all DCD’s Cores are available as a technology independent HDL Source Code, they can be fully customized to best meet customer requirements.
How can I reduce price of a Core ?
You can buy a Netlist License or you can purchase a customized Core without unneeded Core features (peripherals for example).
Have your Cores been verified in hardware?
Yes, all of our Cores are fully tested in hardware and software before public release.
Has DCD's Cores been verified by an independent organization?
Yes, most of DCD’s Cores have ALTERA AMPP Approved or XILINX AllianceCore Flow Checked stamps. It means that core functionality and performance were tested by particular organizations.
Can I evaluate a Core before purchasing?
Yes. DCD offers a free evaluation packages, for particular technologies dependent on the customer requirements. During evaluation customer can check if Core meets desired requirements, and if any modification is needed.
Can I extend the evaluation period?
Each evaluation license is valid for 30 days by default. You can extend the evaluation period without problems for next 30 days. You should just contact sales@dcd.com.pl and ask for new license file.
I noticed that royalties per-chip are not mentioned. Do you charge royalties? If so, when do they apply?
DCD doesn’t charge any royalty fees. Each license is one time paid. It simplifies mutual business and makes live easier for both partners.
What is the cost of some additional Peripherals, 2nd Serial Port, SPI, Watchdog Timer?
You can select custom configuration of the core with additional peripherals, DCD do not charge any fees for customization of the core by adding or removing peripherals/features. Total cost of such core is a sum of modules prices.
What the evaluation package includes?
Typically, evaluation package contains:
Core as
Encrypted ALTERA Megafunction with example project for QUARTUS II tool, or
EDIF netlist component for XILINX technolgy, or
Compiled HDL Source code into ModelSim library format for ASIC packages
Core documentation,
Datasheet,
Installation note,
License file
Do you have any customer reference design? Any silicon proven case for reference?
DCD has a lot of world wide customer. Our cores have been implemented in FPGA and ASIC applications. You may check our reference list on-line. For further details please send us an email.
Is it possible to have a free DI2CM Core license which will allow us to fit our design into an ACEX chip without having the output of programming file?
Yes, the evaluation package of each I2C Core is available for any ALTERA device.
What is delivered wit the Core?
Package is delivered by Express Mail. Delivery to USA usually takes 4 business days. Delivered product package contains:
CD-ROM with ordered IP Core:
Plain text EDIF netlist, VHDL, or VERILOG Source code
VHDL, or VERILOG test bench environments:
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation:
Installation notes
HDL core specification
Instructions set details
Datasheet
Synthesis scripts
Example application
Technical support:
IP Core implementation support
3 months of maintenance:
Delivery the IP Core updates, minor and major versions changes
Delivery the documentation updates
Phone & email support
Printed documentation
Installation notes
Instructions set details
HDL core specification
License agreement
Certificate of Authenticity
If we get HDL source, will it be encrypted or plain text?
An HDL Source package always contains complete Core and Test Bench written as plain text VHDL or VERILOG files.
What the DoCD on-Chip Debug system includes?
DoCD TM is DCD’s own on-chip debug tool. It allows real-time debugging of running software inside hardware (Silicon).
DoCD system includes:
Debug IP Core incorporated into microcontroller core
HAD PCB board (Hardware Assisted Debugger) - used for communication between Debug IP core inside Silicon and Windows Debug Software.
Windows Debug Software - running on Windows operating systems
No, an extra Maintenance is not obligatory. It can be purchased at any time depends on individual customer's needs. Please note that each Licensed Core includes 3 months of Maintenance and Core Implementation support without additional fees.
I'm interested in your DR8051 and DR8051XP Cores, and would like some additional information. In Core datasheets a I have found a feature:
- scan test ready.
What does "scan test" ready mean?
Scan test ready means that the IP Core is developed according to all rules needed for automatic insertion of scan test (for example by Synopsys Design Compiler tool). There are certain rules which should be fulfilled by IP Core, to allow automatic testing at pre-production stage of the complete design.
I’m interested in purchasing of your DR8051 Core. Please send me information about any development tools supported by your Core?
Generally DR8051 can work with most popular 8051 debuggers. However DCD’s has own on-chip debugger called DoCD System (DCD on Chip Debug System). It allows debugging inside hardware (Silicon) and functional simulation of a C/ASM code (Simulator).
DoCD system includes:
Debug IP Core incorporated into microcontroller core
HAD PCB board (Hardware Assisted Debugger) - used for communication between Debug IP core inside silicon and Windows Debug Software.
Windows Debug Software - running on Windows operating systems
For more information please see DoCD TMsoftware page.
I have noticed that you have three I2C bus interfaces, can you please shortly describe differences between particular Core?
The following I2C IP Cores are available:
DI2CM - Master I2C core works in multi-master system with clock synchronization and arbitration features
DI2CS - Slave I2C controller to use with microcontrollers
DI2CSB - Base slave I2C controller to use with passive devices such as LCD displays, pressure sensors etc.
All I2C controllers support: STANDARD, FAST and HIGH SPEED modes and have been widely used by DCD's customers. They are fully compliant to Philips I2C standard, and all its features are incorporated.
Just a clarification of the signal polarity: is the DI2CM SCLHS pin 'high', when the SCL line should be driven 'high'?
Yes, you have right. When SCLHS is high then SCL line should be also driven to logic high. Details are found in DI2CM Core specification.
I have a single question concerning DI2CM core: the 3.4MHz high-speed operation of the I2C bus prescribes an active high-edge drive of the clock signal which is different from lower speeds. Have you implemented this feature with a special Xilinx I/O cell configuration, or is this feature not included in your product ?
High speed DI2CM contains one additional pin required to provide 3.4 Mb transmission. There is no need to use special I/O features of particular technology. Standard I/O can be used to provide High Speed transmissions.
One clarification of the high-speed mode driver in DI2CM Core: how are you implementing the 'current-source pull-up' cell? Can this be done by a particular Virtex OBUFT driver, or is external circuits needed?
The OBUFT can be used as current pull-up source. This pull-up is needed to assure "sharp" clock edges when SCL line is loaded by large capacity.
Which kind of communication is used between PC and DoCDTM. In DoCDTM datasheet is mentioned that the communication uses three wires. Is there an additional hardware used, connected between PC and DoCD?
DoCDTM debug software communicates through Hardware Assisted Debugger (HAD) with Debug IP Core. HAD is a small PCB board assuring appropriate I/O voltage level shifting for different hardware implementation. The following I/O voltage levels are automatically supported:
5 V
3.3 V
2.5 V
What parts of DoCD are scalable?
The following features can be turned on/off before synthesis:
whole DoCD can be turned off after successful debug (when final project is being finalized into an ASIC/FPGA)
each of 4 hardware breakpoints can be turned off (code execution BP, internal data memory BP, external data memory BP, sfr BP)
writing data into internal, external memories or SFRs can be turned off
it works with all DCD's 8051 architectures ( DR8051x, DP8051x, DR80390x, DP80390x)
It allows save a space occupied by the debugger.
Our board has some IIC target chips on the IIC Control chain(mostly from Philips). Was your core tested in this environment? Should I take care about any issue when I place your core with other targets?
Yes, all of our I2C Cores: DI2CSB, DI2CS and DI2CM have been tested on hardware board using Philips
I2C chips (PCF8573, PCF8574, PCF8582) for communication purpose. This product is used also by our customers and is fully validated in silicon.
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