Documentation
The DF6811 is a advanced 8-bit MCU IP Core, with highly sophisticated, on chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller. It has an improved FAST architecture, that is approximately 4 times faster, compared to original implementation. In the standard configuration, the core has integrated on chip, major peripheral functions. The Core can be provided in configurations, that match the following:
- 68HC11A
- 68HC11D
- 68HC11E
There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system, has three input capture lines, five output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem, can count external events, or measure external periods.Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected.Two software-controlled power-saving modes - WAIT and STOP, are available to conserve additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications.
The DF6811E Microcontroller Core can be equipped with the ADC Cotroller, allowing use of external ADC Controller with standard ADC software. The ADC Controller makes external ADC's visible as internal ADC's in original 68HC11E Microcontrollers. The DF6811E has built-in real time, on-chip hardware debugger - DoCDTM, allowing easy software debugging and validation. The DF6811E is fully customizable - it is delivered in the exact configuration to meet users requirements. There is no need to pay extra, for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's DF68XX Core, has a built-in support for DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger
Family summary
| Family | IP Core |
Architecture type |
Memory space | DoCDTM | UART (SCI) | SPI M/S | IO Ports |
Watchdog Timer |
Timer | Compare / Capture |
Pulse accumulator |
READY pin |
Chip Selects | Gatecount |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HC05, HC08 | DF6805 | fast | 64k | + | + | - | 4 | + | 1 | 2/2 | - | + | - | 7000 |
| - | DF6808 | fast | 64k | + | + | - | 4 | + | 1 | 2/2 | - | + | - | 8300 |
| - | D68HC05 | legacy | 64k | + | + | + | 4 | + | 1 | 1/1 | - | - | - | - |
| - | D68HC08 | legacy | 64K | + | + | + | 4 | + | 1 | 2/1 | - | - | - | 10000 |
| HC11 | DF6811E | fast | 64k | + | + | + | 5 | + | 1 | 5/4 | + | + | - | 12000 |
| - | DF6811F | fast | 64k | + | + | + | 7 | + | 1 | 5/4 | + | + | - | 14000 |
| - | DF6811K | fast | 1M | + | + | + | 10 | + | 3 | 13/6 | + | + | - | 21000 |
| - | D68HC11E | legacy | 64k | + | + | + | 5 | + | 1 | 5/4 | + | - | - | 13000 |
| - | D68HC11K | legacy | 1M | + | + | 1 | 10 | + | 3 | 13/6 | + | - | 4 | 21000 |
| - | D68HC11F | legacy | 64k | + | + | + | 7 | + | 1 | 5/4 | - | - | 4 | 13500 |
| 6802, 6803 | DF6802 | fast | 64k | + | - | - | - | - | - | - | - | - | - | - |
| - | DF6803 | fast | 64k | + | + | + | 4 | - | 1 | + | - | - | - | - |
| - | D6802 | legacy | 64k | + | - | - | - | - | - | - | - | - | - | 3600 |
| - | D6803 | legacy | 64k | + | + | + | 4 | - | 1 | + | - | - | - | 6000 |
The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.
Performance
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation |
Speed grade |
Utilized Area [LE / ALUT] |
Frequency [MHz] |
|---|---|---|---|
| CYCLONE II | -6 | 3567 | 54 |
| CYCLONE III | -6 | 3574 | 70 |
| CYCLONE IV | -6 | 3575 | 73 |
| STRATIX II | -3 | 2532 | 100 |
| STRATIX III | -2 | 2501 | 153 |
| STRATIX IV | -2 | 2522 | 135 |
Implementation results for ALTERA devices.
CPU Features
- FAST architecture, 4 times faster than the original implementation
- Software compatible with industry standard 68HC11
- 10 times faster multiplication
- 16 times faster division
- 256 bytes of remapped System Function Registers space (SFRs)
- De-multiplexed Address/Data Bus, to allow easy memory connection
- Core can also be used without I/O wrapper, so each peripheral functions pins will be separated from I/O ports lines.
- Two power saving modes: STOP, WAI
- Ready pin allows Core to operate with slow program and data memories.
- Fully synthesizable
- Static synchronous design
- No internal reset generator or gated clock
- Positive edge clocking and no internal tri-states
- Scan test ready
- 1 GHz of virtual clock frequency compared to original implementation
Symbol
porta portc portd
porte (7:0)
straportb (7:0)
strb
docddatai clkdocddocddatao
docdclk
esieso
esck
ecs
ready databusaddr (15:0)
we
oe
adcdataiadcdatao
adcclock
adccs
xirq irq moda_lir modbe
Pins description
| Pin | Type | Description |
|---|---|---|
| porta | input | Port A pins shared with Timer Input Capture and Output COmpare functions |
| portc | input | Port C - bidirectional I/O Port |
| portd | input | Port D - Bidirectional I/O Portt, shared with SPI and UART functions |
| porte (7:0) | input | Port E - General purpose input port |
| stra | input | Parallel port handshake system - strobe input |
| docddatai | input | DoCDTM serial data input |
| clkdocd | input | Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped). |
| esi | input | Serial Data input - connected to data output pin on EEPROM memory |
| ready | input | READY pin to allow operations with slow memories and peripherals |
| databus | input | Bidirectional non-multiplexed databus to connect external memories. |
| adcdatai | input | Serial ADC data input |
| xirq | input | Non-maskable interrupt request |
| irq | input | Maskable interrupt request |
| moda_lir | input | MODA pin input shared with LIR output |
| modb | input | Mode B input |
| portb (7:0) | output | Port B output lines |
| strb | output | Parallel port handsake system - strobe output |
| docddatao | output | DoCDTM serial data output |
| docdclk | output | DoCDTM serial data clock line |
| eso | output | Serial data output - connected to data input on EEPROM Memory |
| esck | output | EEPROM SPI Clock line |
| ecs | output | EEPROM Chip Select |
| addr (15:0) | output | Non-multiplexed address bus to connect external memories |
| we | output | Write enable to external memories |
| oe | output | Output enable to external memories |
| adcdatao | output | Serial ADC data output |
| adcclock | output | Serial clock to ADC devices |
| adccs | output | Serial ADC chip select line |
| e | output | E Clock output |
Block Diagram
| IO PortsGeneral Purpose I/O Ports, when enabled the I/O Ports are shared with particular on chip peripherals: SCI, SPI, TIMER. |
porta
portb (7:0)
portc
portd
porte (7:0)
stra
strb
| DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off. The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped). |
docddataidocddataodocdclkclkdocd
| EEPROMCTRLExternal Serial EEPROM controller. This optional module, manages data exchange between D68HC11 and external EEPROM. During initialization, it copies contents of the whole external EEPROM, to internal EEPRAM (EEPROM Mirror implemented in standard parallel RAM). This module has several different options, therefore its details have been described in a separate document. |
esiesoesckecs| TIMERMain Timer system, including Compare, Capture and Real Time Interrupt logic.
This timer system is based on a free-running, 16-bit counter, with a 4-stage programmable prescaler. A timer overflow function allows software, to extend the timing capability of the system, beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time, when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals, or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in more detail. A programmable periodic interrupt circuit (RTI) is tapped off the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer, in which the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain. The timer subsystem involves more registers and control bits, than any other subsystem on the MCU. Each of the three input-capture functions, has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions, has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit the software, to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications, although it is not as efficient as a dedicated hardware, for some specific timing applications. |
| BUSCTRLMemory and SFR's (Special Function Register) interface controls access into the Internal/External program and data memories and special function registers. Address and Dabaus lines are non-multiplexed to allow fast memory operations, required by enhanced fast CPU. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic. |
ready
databusaddr (15:0)weoe| ADC ControllerThe ADCCTRL used in D68HC11, provides communication between the internal ADC related registers and program running on D68HC11 and external ADC converter. Supports several Parallel and serial ADC. |
adcdatai
adcdatao
adcclock
adccs
| SPIIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of Serial Clock Signal (SCK). It enables the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor communications, in a multi-master system. The Serial Clock Line (SCK) synchronizes shifting and sampling of the information, on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data rates are as high, as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector, automatically disables SPI output drivers, if more than one SPI devices simultaneously attempt to become a bus master. |
| SCIThe SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore, the differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and major logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. The logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, which can be used in applications with a modem. |
| PULSEACCAThis system is based on an 8-bit counter and can be configured to operate as a simple event counter or as a tool for gated time accumulation. Unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). Control bits allow the user to configure and control the pulse accumulator subsystem. Two maskable interrupts are associated with the system, each having its own controls and interrupt vector. The PAI pin associated with the pulse accumulator, can be configured to act as a clock (event counting mode) or as a gate signal, to enable a free-running of E divided by 64 clock, to the 8-bit counter (gated time accumulation mode). The alternate functions of the PAI (Pulse Accumulator Input) pin, present some interesting application possibilities. |
| Interrupt ControllerD68HC11 has implemented 17-level interrupt priority control. External interrupt pins are activated at low level (XIRQ, IRQ pins) or falling edge (IRQ pin). External interrupt requests by IRQ and XIRQ, are sampled each 1 system clock at the rising edge of CLK. The D68HC11 peripheral systems generate maskable interrupts, which are recognized only, if the global interrupt mask bit (I) in the CCR, is cleared. Maskable interrupts are prioritized according to default arrangement (look at the table below), established during reset. However, any source may be elevated to the highest maskable priority position, by using HPRIO register. When interrupt condition occurs, an interrupt status flag is set to indicate the condition. |
xirq
irq
| CTRLUNITPerforms the core synchronization and data flow control. This module manages execution of all instructions. |
moda_lirmodbe
| COPCOP Watchdog Timer |
| Data bus Internal 8-bit data bus. |
| SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture. |
Units
IO Ports
General Purpose I/O Ports, when enabled the I/O Ports are shared with particular on chip peripherals: SCI, SPI, TIMER.DoCDTM
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).
EEPROMCTRL
External Serial EEPROM controller. This optional module, manages data exchange between D68HC11 and external EEPROM. During initialization, it copies contents of the whole external EEPROM, to internal EEPRAM (EEPROM Mirror implemented in standard parallel RAM). This module has several different options, therefore its details have been described in a separate document.TIMER
Main Timer system, including Compare, Capture and Real Time Interrupt logic. This timer system is based on a free-running, 16-bit counter, with a 4-stage programmable prescaler. A timer overflow function allows software, to extend the timing capability of the system, beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time, when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals, or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in more detail.A programmable periodic interrupt circuit (RTI) is tapped off the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer, in which the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain.
The timer subsystem involves more registers and control bits, than any other subsystem on the MCU. Each of the three input-capture functions, has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions, has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit the software, to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications, although it is not as efficient as a dedicated hardware, for some specific timing applications.