Documentation
The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface between a microprocessor/microcontroller and the I2C bus. It can work as a master transmitter or a master receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and high-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CM is a technology independent design, that can be implemented in a variety of process technologies.
Family summary
| Design | I2C specification | Operation type | Standard mode | Fast mode | Fast Plus mode | High Speed mode | Multi master | 7 bit address | 10 bit address | Interrupt gen. | Passive elements interface | Microcontroller interface | User defined timing |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 100 kb/s | 400 kb/s | 1 Mb/s | 3.4 Mb/s | ||||||||||
| DI2CM | v3.0 | MASTER | + | + | + | + | + | + | + | + | - | + | + |
| DI2CMS | v3.0 | MASTER/SLAVE | + | + | + | + | + | + | + | + | - | + | + |
| DI2CS | v3.0 | SLAVE | + | + | + | + | + | + | - | + | - | + | + |
| DI2CSB | v3.0 | SLAVE | + | + | + | + | + | + | - | - | + | - | - |
The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping you to find the most suitable IP Core for the application.
Performance
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation |
Speed grade |
Utilized Area [LUT/PFU] |
Frequency [MHz] |
|---|---|---|---|
| EC | -5 | 340 / 120 | 185 |
| ECP | -5 | 340 / 120 | 183 |
| XP | -5 | 340 / 120 | 155 |
| ECP2 | -7 | 285 / 120 | 253 |
| ECP2M | -7 | 239 / 120 | 253 |
| SC | -7 | 295 / 124 | 301 |
| XP2 | -7 | 239 / 120 | 210 |
DI2CM implementation results for LATTICE devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [Slices] |
Frequency [MHz] |
|---|---|---|---|
| VIRTEX-6 | -2 | 69 | 380 |
| VIRTEX-5 | -2 | 108 | 395 |
| VIRTEX-4 | -12 | 158 | 283 |
| VIRTEX-II | -6 | 180 | 198 |
| VIRTEX-E | -8 | 180 | 137 |
| VIRTEX | -6 | 180 | 105 |
| SPARTAN-6 | -4 | 79 | 240 |
| SPARTAN-3E | -5 | 191 | 160 |
| SPARTAN-3 | -5 | 191 | 160 |
| SPARTAN-IIE | -7 | 188 | 125 |
| SPARTAN-II | -6 | 180 | 108 |
DI2CM implementation results for XILINX devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [LC] |
Frequency [MHz] |
|---|---|---|---|
| CYCLONE | -6 | 241 | 250 |
| STRATIX | -5 | 241 | 254 |
| CYCLONE II | -6 | 244 | 263 |
| STRATIX II | -3 | 205 | 380 |
| MAX 2 | -3 | 241 | 187 |
| MAX3000A | -7 | 137 | 49 |
| STRATIX III | -2 | 204 | 430 |
| CYCLONE III | -6 | 258 | 280 |
| STRATIX IV | -2 | 204 | 430 |
DI2CM implementation results for ALTERA devices.
All features have been included.
Key Features
- Conforms to v.3.0 of the I2C specification
- Master operation
- Master transmitter
- Master receiver
- Support for all transmission speeds
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Arbitration and clock synchronization
- Support for multi-master systems
- Support for both 7-bit and 10-bit addressing formats on the I2C bus
- Interrupt generation
- Build-in 8-bit timer for data transfers speed adjusting
- Host side interface dedicated for microprocessors/microcontrollers
- User-defined timing (data setup, start setup, start hold, etc.)
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Applications
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Cost-effective reliable automotive systems
Symbol
rst clk scli sdai
datai (7:0) rd we address (1:0) csPins description
| Pin | Type | Description |
|---|---|---|
| rst | input | Global reset |
| clk | input | Global clock |
| scli | input | I2C bus clock line (input) |
| sdai | input | I2C bus data line (input) |
| datai (7:0) | input | Processor data bus (input) |
| rd | input | Processor read strobe |
| we | input | Processor write strobe |
| address (1:0) | input | Processor address lines |
| cs | input | Chip select |
| sclo | output | I2C bus clock line (output) |
| sclhs | output | High-speed clock line (output) |
| sdao | output | I2C bus data line (output) |
| datao (7:0) | output | Processor data bus (output) |
| irq | output | Processor interrupt line |
Block Diagram
| TimerTimer allows operation from a wide range of the input frequencies. It is programmed by user before transmission and can be reprogrammed to change the SCL frequency. |
| Clock UnitClock Unit performs generation of the serial SCL clock. It is responsible for input spike filtering, clock synchronization and arbitration during operations in multi-master systems. |
| Control LogicControl Logic manages execution of all commands sent via interface. Synchronizes internal data flow. Includes Control Register used for performing all types of I2C Bus transmissions, and Status Register indicates state of the I2C Bus and the DI2CM core. |
| Data UnitIt controls SDA line, performs data and address shifts during the data transmission and reception. Input data spikes are also filtered. |
| CPU InterfaceCPU Interface performs the interface functions between DI2CM internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system. |
datai (7:0)datao (7:0)rdweaddress (1:0)csirq
| DI2CM data DI2CM data bus |