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DSPI FIFO

Serial Peripheral Interface – Master/Slave with FIFO

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    The DSPI_FIFO is a fully configurable SPI master/slave device, which allows you to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with serial peripheral devices but also to communicate interprocessor in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines.
    The DSPI_FIFO data are simultaneously transmitted and received. What's more important, this is technology independent design, that can be easily implemented in a variety of process technologies. The DSPI_FIFO system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as master or slave device with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.

    The DSPI_FIFO automatically drive selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write collision detector indicates when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI devices simultaneously attempts to become bus master.
    The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
    Our solution is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

    The DSPI_FIFO is a technology independent design that can be implemented in a variety of process technologies.


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade    		 Area
    [TILES]    		 Frequency
    [MHz]
    FUSION - 696 86
    ProASIC3 - 698 86
    ProASIC3e - 698 86
    IGLOO - 698 44
    IGLOOe - 698 44

    DSPI_FIFO implementation results for ACTEL devices. 

    Implementation Speed
    grade    		 Area
    [LUT/PFU]    		 Frequency
    [MHz]
    EC - 503/169 115
    ECP - 503/169 104
    XP - 503/169 95
    ECP2 - 502/169 161
    ECP2M - 315/163 162
    SC - 507/164 268
    XP2 - 315/163 132

    DSPI_FIFO implementation results for LATTICE devices. All features have been included. 


    Implementation Speed
    grade    		 Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-III - 185 99
    SPARTAN-IIIE - 194 106
    SPARTAN-IIIAN - 194 108
    SPARTAN-VI - 144 153
    VIRTEX-E - 185 99
    VIRTEX-II - 185 158
    VIRTEX-II pro - 185 170
    VIRTEX-IV - 188 196
    VIRTEX-V - 190 200

    DSPI_FIFO implementation results for XILINX devices.

    Implementation Speed
    grade    		 Area
    [LCE] [ALUT / REG]    		 Frequency
    [MHz]
    CYCLONE 281 181
    CYCLONE-II 282 189
    CYCLONE-III 279 178
    CYCLONE-IV 388 242
    STRATIX 281 195
    STRATIX-II 257 331
    STRATIX-III 253 310
    STRATIX-IV 313 / 229 356

    DSPI_FIFO implementation results for ALTERA devices. All features have been included. 


    Key Features
    • SPI Master
      • Master and Multi-master operations
      • Two modes of operation: SPI mode and FIFO mode
      • 8 SPI slave select lines
      • System error detection
      • Mode fault error
      • Write collision error
      • Interrupt generation
      • Supports speeds up 1/4 of system clock
      • Bit rates generated 1/4 - 1/512 of system clock.
      • Four transfer formats supported
      • Simple interface allows easy connection to microcontrollers
    • SPI Slave
      • Slave operation
      • Two modes of operation: SPI mode and FIFO mode
      • System error detection
      • Interrupt generation
      • Supports speeds up 1/4 of system clock
      • Simple interface allows easy connection to microcontrollers
      • Four transfer formats supported
    • Fully synthesizable
    • Two DMA Modes allows single and multi-transfer
    • In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
    • Optional FIFO size extension to 128, 256 or 512 Bytes
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

    Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Digital multimeters

    Symbol

     mi
     si
    mo 
    so 
    rxrdy 
    txrdy 
     datai (7:0)
     rd
     wr
     addr (1:0)
     cs
    datao (7:0) 
     ss
    scken 
    sso (7:0) 
    int 
    soen 
     scki
    scko 

    Pins description
    PinTypeDescription
    miinputMaster serial data input
    siinputSlave serial data input
    datai (7:0)inputData bus input
    rdinputProcessor read strobe
    wrinputProcessor write strobe
    addr (1:0)inputProcessor address lines
    csinputChip select
    ssinputSlave select
    sckiinputSPI clock input
    mooutputMaster serial data output
    sooutputSlave serial data output
    rxrdyoutputReceiver ready output
    txrdyoutputTransmitter ready output
    datao (7:0)outputData bus output
    sckenoutputSPI clock output enable
    sso (7:0)outputSlave select outputs
    intoutputInterrupt request
    soenoutputSlave output enable
    sckooutputSPI clock output

    Block Diagram
    Shift registerShift register is a core element of every SPI system. It is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter, until the previous transaction is complete. However, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer, before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. There is also another way to view this transfer, while 8-bit shift register in the master and another 8-bit shift register in the slave are connected, as a circular 16-bit shift register. When transfer occurs, this distributed shift register is moved 8-bit positions; thus, the characters in the master and slave are effectively exchanged.
    mi
    mo
    si
    so
    RX FIFOThe Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO, equals the selected interrupt trigger level. At that time, if interrupt is enabled, the DSPI_FIFO will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Over-run Error flag.
    TX FIFOThe Tx portion of the DSPI_FIFO transmits data through SO/MO, as soon as the CPU loads a byte into the Tx FIFO in Master mode. In Slave mode, the transmission is started after correct edge of the SCK signal. The DSPI_FIFO will prevent loads to the Tx FIFO, if it currently holds 64 (128, 256, 512) characters (depending on SFCR [5] bit value and selected FIFO size). Loading to the Tx FIFO again will be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.
    DMA ControllerTXRDY, RXRDY - thanks to these two pinsTransmitter and Receiver DMA signaling are available. When operating in the FIFO mode, one of two types DMA signaling per pin can be selected via SFCR3. When operating, as in the SPI Mode, only DMA mode 0 is allowed. Mode 0 supports then single transfer DMA, where a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA, where multiple transfers are made continuously until the RCVR FIFO has been emptied or the XMIT FIFO has been filled.
    rxrdy
    txrdy
    Control RegistersThe Control Registers module contains all DSPI internal data, control and status registers.

    SPI Data Register (SPDR) is in fact double register - write only transmitter data register and read only receiver data register.

    Control Register may be read or written at any time, is used to configure the DSPI system. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed.

    Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence.

    Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts.

    FIFO Control Register (FCR) available only in DSPI_FIFO mudule equipped with the FIFOs transmitter and receiver. FCR contains control bit, which configure receiver trigger level, enables FIFO mode, defines FIFO size and enables DMA mode.
    datai (7:0)
    datao (7:0)
    rd
    wr
    addr (1:0)
    cs
    SPI ControllerThe SPI Controller manages the Master/Slave operation and controls the transmission. It also manages the transmission speed and format (Phase and polarity). Controller itself generates interrupt request and detects transmission errors.
    scken
    ss
    sso (7:0)
    int
    soen
    SPI Clock LogicSoftware can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.
    scki
    scko
    SPI bus SPI virtual bus

    Units
    Shift register
    Shift register is a core element of every SPI system. It is single buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter, until the previous transaction is complete. However, received data is transferred into a parallel read data buffer, so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer, before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin, while a different 8-bit character is simultaneously shifted in a second data pin. There is also another way to view this transfer, while 8-bit shift register in the master and another 8-bit shift register in the slave are connected, as a circular 16-bit shift register. When transfer occurs, this distributed shift register is moved 8-bit positions; thus, the characters in the master and slave are effectively exchanged.
    RX FIFO
    The Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO, equals the selected interrupt trigger level. At that time, if interrupt is enabled, the DSPI_FIFO will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Over-run Error flag.
    TX FIFO
    The Tx portion of the DSPI_FIFO transmits data through SO/MO, as soon as the CPU loads a byte into the Tx FIFO in Master mode. In Slave mode, the transmission is started after correct edge of the SCK signal. The DSPI_FIFO will prevent loads to the Tx FIFO, if it currently holds 64 (128, 256, 512) characters (depending on SFCR [5] bit value and selected FIFO size). Loading to the Tx FIFO again will be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.

    DMA Controller
    TXRDY, RXRDY - thanks to these two pinsTransmitter and Receiver DMA signaling are available. When operating in the FIFO mode, one of two types DMA signaling per pin can be selected via SFCR3. When operating, as in the SPI Mode, only DMA mode 0 is allowed. Mode 0 supports then single transfer DMA, where a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA, where multiple transfers are made continuously until the RCVR FIFO has been emptied or the XMIT FIFO has been filled.
    Control Registers
    The Control Registers module contains all DSPI internal data, control and status registers.

    SPI Data Register (SPDR) is in fact double register - write only transmitter data register and read only receiver data register.

    Control Register may be read or written at any time, is used to configure the DSPI system. This register controls the mode of transmission (Master, Slave), polarity and phase of SPI Clock and transmission speed.

    Status Register (SPSR) contains flags, indicating the completion of transfer or occurrence of system errors. All flags are set automatically when the corresponding event occur and cleared by software sequence.

    Slave Select Control Register configures which slave select output should be driven while SPI master transfer. Contents of SSCR register is automatically assigned on SS7O-SS0O pins when DSPI master transmission starts.

    FIFO Control Register (FCR) available only in DSPI_FIFO mudule equipped with the FIFOs transmitter and receiver. FCR contains control bit, which configure receiver trigger level, enables FIFO mode, defines FIFO size and enables DMA mode.
    SPI Controller
    The SPI Controller manages the Master/Slave operation and controls the transmission. It also manages the transmission speed and format (Phase and polarity). Controller itself generates interrupt request and detects transmission errors.

    SPI Clock Logic
    Software can select any from four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers, to allow master device communication with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.