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D16550

Configurable UART with FIFO

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    The D16550 is a soft Core of Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C550A. It allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both, receive and transmit directions. The D16550 performs serial-to-parallel conversion on data characters, received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters, received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. Reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt).
    The D16550 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. Our soft core has a complete MODEM control capability and a processor-interrupt system. What's more important, interrupts can be programmed to user's requirements, minimizing the computing required to handle the communication link.
    A separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency. Configuration capability allows the user to enable or disable during the Synthesis process the Modem Control Logic and FIFO's or change the FIFO's size. So, in applications with an area limitation and where the UART works only in the 16450 mode, disabling of Modem Control and FIFO's allow to save about 50% of logic resources.
    Our trustworthy Core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. We recommend it also for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, the D16550 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.

    The D16550 includes fully automated testbench with a complete set of tests, allowing easy package validation at each stage of SoC design flow. Please remember, that our soft core is a technology independent design, that can be implemented in a variety of process technologies.


    Family summary

    UART Feature DμART D2692 D16450 D16550 D16750 D16552 D16752 D16950
    FIFO Size - 2*8 - 2*16 2*64 4*16 x*2*64 2*128
    Multichannel option - - - - - + + -
    Separate BAUD Clock line + - + + + + + +
    Modem Control - - + + + + + +
    False Start Bit detection + + + + + + + +
    Status report + + + + + + + +
    Internal diagnostic capabilities + + + + + + + +
    Prioritized interrupt system - + + + + + + +
    Break generation and detection - + + + + + + +
    Fast mode CLK/4 - - - - o - o +
    Half-Duplex RS485 - + - - o - o +
    RS485 buffer enable - - - + + - + +
    IRDA support - - - - o + - +
    Additional CLK prescaler - - - - - - + -
    1284 Parallel Port - - - - - + - -
    Hardware flow control RTS/CTS - + - - + - + +
    Software flow control Xon/Xoff - - - - - - + +
    Isochronous mode - - - - - - - +
    Detector of bad data in receiver FIFO - + - + + + + +
    Special character detection - - - - - - + +
    Software channel reset - - - - - - - +
    4 byte device ID - - - - - - - +
    Trigger levels for receiver and transmitter - - - - - - - +
    Hardware flow control DTS/DTR - - - - - - - +
    Optional FIFO size extension to 512 bytes - - - - + - + -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Area
    [TILES]    		 Frequency
    [MHz]
    FUSION 1109 93
    ProASIC3 1109 96
    proASIC3E 1109 94
    IGLOO 1109 65
    IGLOO+ 1109 63
    IGLOOe 1135 49

    Implementation results for ACTEL devices. 

    Implementation Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-IIE 267+2RAM 100
    SPARTAN-III 267+2RAM 122
    SPARTAN-IIIE 272+2RAM 90
    VIRTEX-E 267+2RAM 100
    VIRTEX-II 264+2RAM 168
    VIRTEX-II pro 268+2RAM 190
    VIRTEX-IV 272+2RAM 201
    VIRTEX-V 274+2RAM 218

    Implementation results for XILINX devices.  


    Implementation Area
    [LUT/PFU]    		 Frequency
    [MHz]
    EC 569 / 239 166
    ECP 569 / 239 143
    XP 569 / 239 130
    ECP2 529 / 232 177
    ECP2M 410 / 228 177
    SC 541 / 232 253
    XP2 410 / 227 130

    Implementation results for LATTICE devices. 

    Implementation Speed
    grade    		 Area
    [LC]    		 Memory
    Bits    		 Frequency
    [MHz]
    ARIA GX -6 342/231 304 243
    ARIA V -6 330/263 304 209
    CYCLONE -6 465 304 193
    CYCLONE II -6 476 304 220
    CYCLONE III -6 477 304 250
    CYCLONE IV -6 478 304 250
    CYCLONE V -6 328/231 304 187
    STRATIX -5 465 304 206
    STRATIX II -3 342/232 304 343
    STRATIX III -2 334/231 304 527
    STRATIX IV -2 330/250 304 497
    STRATIX V -2 332/262 304 456
    STRATIX GX -5 465 304 214
    STRATIX 2 GX -3 340/231 304 341

    Implementation results for ALTERA devices.  


    Key Features
    • Software compatible with 16450 and 16550 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    • Supports RS232 and RS485 standards
    • Two modes of operation: UART mode and FIFO mode
      • In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
      • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud generator
    • Independent receiver clock input
    • MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
    • Fully programmable serial interface characteristics:
      • 5-, 6-, 7-, or 8-bit characters
      • Even, odd or no-parity bit generation and detection
      • 1-, 1 ½-, or 2-stop bit generation
      • Internal baud generator
    • Complete status reporting capabilities
    • Line break generation and detection. Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Configuration

    The following parameters of the D16550 core can be easily adjusted to the requirements of dedicated application and technology. Core configuration can be effortlessly done, by changing appropriate constants in package file. There is no need to change any part of the code.

    • Baud generator: enable / disable
    • External RCLK source: enable / disable
    • External BAUDCLK source: enable / disable
    • Asynchronous input buffer: enable / disable
    • Modem Control: enable / disable
    • SCR register: enable / disable
    • FIFO Control logic: enable / disable
    • FIFO's size: 2 / 4 / 8 / 16 - default

    Symbol

     clk
     rst
    so 
    temt 
     rclk
     si
     cts
     dsr
     dcd
     ri
    rts 
    dtr 
    out1 
    out2 
    intr 
     datai (7:0)
     rd
     wr
     cs
     addr (2:0)
    datao (7:0) 
    ddis 
    txrdy 
    rxrdy 
     baudclken
     baudclk
    baudout 

    Pins description
    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    rclkinputReceiver clock
    siinputSerial data input
    ctsinputClear to send input
    dsrinputData set ready input
    dcdinputData carrier detect input
    riinputRing indicator input
    datai (7:0)inputParallel data input
    rdinputRead input
    wrinputWrite input
    csinputChip select
    addr (2:0)inputAddress bus
    baudclkeninputBaud generator clock enable
    baudclkinputBaud generator clock
    sooutputSerial data output
    temtoutputTransmitter Empty - used to control RS485 buffer
    rtsoutputRequest to send output
    dtroutputData terminal ready output
    out1outputOutput 1
    out2outputOutput 2
    introutputInterrupt request output
    datao (7:0)outputParallel data output
    ddisoutputDriver disable output
    txrdyoutputTransmitter ready output
    rxrdyoutputReceiver ready output
    baudoutoutputBaud generator output

    Block Diagram
    Transmitter ControlTransmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    so
    temt
    Transmitter FIFOThe Tx portion of the UART transmits data through SO, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it is currently full. Loading to the Tx FIFO will be enabled again, as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.
    Receiver ControlThe D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.
    rclk
    si
    Receiver FIFOThe Rx FIFO is 16 levels (16550), 64 levels (16750) or 128 levels (16950) deep. It receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. These data entering the Rx shift register will set the Overrun Error flag.
    Modem Control LogicModem Control Logic monitors the interface with the MODEM, data set or a peripheral device emulating MODEM.
    rts
    cts
    dtr
    dsr
    dcd
    ri
    out1
    out2
    Interrupt ControllerD16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.
    intr
    Data Bus BufferData Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low and qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    datai (7:0)
    datao (7:0)
    rd
    wr
    cs
    ddis
    txrdy
    rxrdy
    addr (2:0)
    Baud GeneratorThe UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.
    baudout
    baudclken
    baudclk
    clk
    rst
    D16550 D16XXX UART internal data bus

    Units
    Transmitter Control
    Transmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    Transmitter FIFO
    The Tx portion of the UART transmits data through SO, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it is currently full. Loading to the Tx FIFO will be enabled again, as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.
    Receiver Control
    The D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is being detected. After starting, the SI input is sampled every 16 RCLK cycles, as it is shown in figure below. When the logic 1 state is detected during START bit, it means that the False Start bit was detected and receiver back to the IDLE state.

    Receiver FIFO
    The Rx FIFO is 16 levels (16550), 64 levels (16750) or 128 levels (16950) deep. It receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. These data entering the Rx shift register will set the Overrun Error flag.
    Modem Control Logic
    Modem Control Logic monitors the interface with the MODEM, data set or a peripheral device emulating MODEM.
    Interrupt Controller
    D16X50 UARTs got fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.

    Data Bus Buffer
    Data Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low and qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.
    Baud Generator
    The UART contains a programmable 16 bit baud generator, that divides clock input by a divisor, in the range between 1 and (216-1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

    divisor=frequency/(16*baudrate)

    Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM, to prevent long counts on initial load.