Digital Core Design

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DFPMUL

Floating Point Pipelined Multiplier Unit

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    The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers' format has been developed according to IEEE-754 standard. Our rigorous IP Core supports a single precision real number. Multiply operation was pipelined up to 7 levels and input data is fed every clock cycle. The first result appears after latency depending on pipeline level and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included.
    The DFPMUL is a technology independent design, that can be implemented in a variety of process technologies.


    Family summary

    Design Standard compliance Operation Input data Output data NORMAL numbers DENORMAL, NaNs, INFINITY Pipeline levels Single clock result Initial latency
    DFPADD IEEE-754 Addition Single precision real Single precision real + + 5 + 5
    DFPMUL IEEE-754 Multiplication Single precision real Single precision real + + 7 + 7
    DFPDIV IEEE-754 Division Single precision real Single precision real + + 15 + 15
    DFPSQRT IEEE-754 Square root Single precision real Single precision real + + 9 + 9
    DFPCOMP IEEE-754 Compare Single precision real Single precision real + + 1 + 1
    DFP2INT IEEE-754 FP to Integer conversion Single precision real Integer + + 2 + 2
    DINT2FP IEEE-754 Integer to FP conversion Integer Single precision real + + 3 + 3

    The main features of each Floating Point Units family member has been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application. Please see also the Arithmetic Coperocessors: DFPMU, DFPMU-DP and DFPAU , DFPAU-DP

    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade    		 Utilized Area
    [LUT/PFU]    		 Frequency
    [MHz]
    ispXPGA -4 1472/580 44
    EC -5 1800/ - 45
    ECP -5 1244/ - 59

    DFPMUL implementation results for LATTICE devices.
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-IIE -7 488 57
    SPARTAN-3 -5 222+4M1 76
    SPARTAN-3E -4 222+4M1 67
    VIRTEX-E -8 520 60
    VIRTEX-II -6 222+4M1 98
    VIRTEX-II pro -7 222+4M1 115
    VIRTEX-4 -12 255+4M2 183

    1- MULT18X18 block   2- DSP48 block   DFPMUL implementation results for XILINX devices.
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [LC]    		 Frequency
    [MHz]
    APEX20KC -7 1210 51
    STRATIX -5 440+8M1 93
    CYCLONE -6 1170 72
    STRATIX II -3 410+8M1 134
    CYCLONE-II -6 480+8M1 117

    1- 9-bit DSP bock  DFPMUL implementation results for ALTERA devices.
    All features have been included. 


    Key Features
    • Full IEEE-754 compliance
    • Single precision real format support
    • Simple interface
    • No programming required
    • 7 levels pipeline
    • Overflow, underflow and invalid operation flags
    • Full accuracy and precision
    • Results available at every clock
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

    Applications

    • Math coprocessors
    • DSP algorithms
    • Embedded arithmetic coprocessor
    • Fast data processing & control

    Symbol

     adatai (31:0)
     bdatai (31:0)
    datao (31:0) 
    ofo 
    ufo 
    ifo 

    Pins description
    PinTypeDescription
    adatai (31:0)inputA data bus input
    bdatai (31:0)inputB data bus input
    datao (31:0)outputData bus output
    ofooutputOverflow flag
    ufooutputUnderflow flag
    ifooutputInvalid flag

    Block Diagram
    Main FP Pipelined UnitIt performs floating point multiply function, giving the complex information about the results and making final flags settings.
    Arguments CheckerIt performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.
    adatai (31:0)
    bdatai (31:0)
    Result ComposerIt performs result rounding function, data alignment to IEEE-754 standard and the final flags setting.
    datao (31:0)
    ofo
    ufo
    ifo
    FP output Output bus used for data transfer

    Units
    Main FP Pipelined Unit
    It performs floating point multiply function, giving the complex information about the results and making final flags settings.
    Arguments Checker
    It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.
    Result Composer
    It performs result rounding function, data alignment to IEEE-754 standard and the final flags setting.