The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Its content is accessible to CPU, in the same manner as common SRAM memory but requires READY input to expand time access. Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory. The controller automatically sends all control instructions and read - write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it's visible and controlled as parallel SRAM with long access time. Our unique Core has been designed to operate with popular 25XXX SPI Serial EEPROMs (Atmel, Microchip).
Key Features
- Standard memory interface with ready control
- Configurable SPI parameters
- Serial clock prescaler
- SPI mode
- CS hold/setup
- Updating bits in EEPROM status register
- Simple interface allows easy connection to microcontrollers
- Fully synthesizable, static design with no internal tri-states
Applications
Applcations requiring data storage in external non-voltile memories.
Symbol
addr (15:0)
datai (7:0)
wr
rd
cs
datao (7:0)
ready
esi
Pins description
| Pin | Type | Description |
|---|
| addr (15:0) | input | Micrcprocessor address bus |
| datai (7:0) | input | Data Bus input |
| wr | input | Write signal |
| rd | input | Read input |
| cs | input | Chip select |
| esi | input | EEPROM serial data input |
| datao (7:0) | output | Databus output |
| ready | output | Ready signal |
| eso | output | Serial data output |
| eck | output | Serial clock |
| ecs | output | EEPROM Chip Select |
Block Diagram
| Control UnitControl Unit manages execution of all commands sent via interface. Synchronizes internal data flow. |
| CPU InterfaceThe CPU Interface manage bada exchange between CPU and DEEPROMCTRL. It allows parallel data to be written to and read from DEEPROMCTRL and transfered serial to/from external serial EEPROM Memory. |
addr (15:0)
datai (7:0)
datao (7:0)
wr
rd
cs
ready
| EEPOM InterfaceEEPROM interface manages serial data exchange between DEEPROMCTRL and external serial EEPROM. |
| Internal data bus 8-bit internal data bus |
Units
Control Unit
Control Unit manages execution of all commands sent via interface. Synchronizes internal data flow.
CPU Interface
The CPU Interface manage bada exchange between CPU and DEEPROMCTRL. It allows parallel data to be written to and read from DEEPROMCTRL and transfered serial to/from external serial EEPROM Memory.
EEPOM Interface
EEPROM interface manages serial data exchange between DEEPROMCTRL and external serial EEPROM.