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The DP80C51 is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. The DP80C51 soft core is 100% binary and pin compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the DP80C51: Harvard, where external data and program buses are separated, and von Neumann, with common program and external data bus. The DP80C51 has a Pipelined RISC architecture, up to 10 times faster, comparing to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP80C51 is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
Each of the DCD's 8051 Core has a built-in support for DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. More details about DCD on Chip Debugger
The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
DP80C51 implementation results for LATTICE devices. The CPU features and Peripherals have been included.
DP80C51 implementation results for XILINX devices. The CPU features and Peripherals have been included.
DP80C51 implementation results for ALTERA devices. The CPU features and Peripherals have been included.
- Pin in 100% compatible with industry standard 8051
- Software in 100% compatible with industry standard 8051
- Pipelined RISC architecture
- 10 times faster, compared to 8051 standard
- 24 times faster multiplication
- 12 times faster division
- Up to 256 bytes of internal (on-chip) Data Memory
- Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
- Up to 64 kB of external (off-chip) Data Memory
- User programmable Program Memory Wait States
- User programmable External Data Memory Wait States
- Dedicated signal for Program Memory writes
- Interface for additional Special Function Registers
- Fully synthesizable, static synchronous design, with positive edge clocking and no internal tri-states
- Scan test ready
- 2 GHz virtual clock frequency in a 0.25u technological process
|ramdatai (7:0)||input||Data bus from internal data memory|
|tdi||input||DoCDTM TAP data input|
|tck||input||DoCDTM TAP clock line|
|tms||input||DoCDTM TAP mode select|
|sfrdatai (7:0)||input||Data bus from user SFRs|
|prgramdata (7:0)||input||Data bus from internal RAM program memory|
|prgromdata (7:0)||input||Data bus from internal ROM program memory|
|ea||input||Enable all external program memory|
|port0 (7:0)||output||Port 0 bus, Data/LSB address of external memory|
|port1 (7:0)||output||Port 1 bus|
|port2 (7:0)||output||Port 2 bus, MSB address of external memory|
|port3 (7:0)||output||Port 3 bus, mutlifunctional pins|
|ramdatao (7:0)||output||Data bus for internal data memory|
|ramaddr (7:0)||output||RAM address bus|
|ramoe||output||Internal data memory read|
|ramwe||output||Internal data memory write enable|
|stop||output||Stop mode indicator|
|pmm||output||Power management mode indicator|
|tdo||output||DoCDTM TAP data output|
|rtck||output||DoCDTM return clock|
|sfrdatao (7:0)||output||Data bus for user SFRs|
|sfrwe||output||User SFRs write enable|
|sfroe||output||User SFRs read|
|sfraddr (6:0)||output||User SFRs address bus|
|prgaddr (15:0)||output||Internal program memory address bus|
|prgdatao (7:0)||output||Data bus for internal program memory|
|prgramwr||output||Internal program memory write|
|ale||output||Address Latch Enable|
|psen||output||Program Store (memory) read Enable|
|pswr||output||Program Store (memory) Write|
|Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.|
|Control UnitPerforms the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.|
|TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as a clock source for UARTs. Please note, that external pins of this module are connected to appropriate pins of P3 port.|
|UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 syn-chronous modes. UART0 can be synchronized by Timer 1. Please note, that external pins of this module are connected to appropriate pins of P3 port.|
|I/O PortsBlock contains 8051's general purpose I/O ports. Each of port's pin can be read/written as a single bit or as a 8-bit bus P0, P1, P2, P3. The P0, P2, P3 are multi-functional ports. When used with External memory P0 works as a multiplexed Data/LSB address to memory, and P2 works as a MSB address to external memory, P3.6 is a write signal and P3.7 is a read signal. Functionality of port is the same as in legacy 80C51 microcontroller.|
|Internal Data Memory InterfaceInterface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.|
|ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.|
|Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.|
|DoCDTM JTAG DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.|
|SFRs InterfaceSpecial Function Registers interface - controls access to externally connected peripherals, through SFR bus.|
|Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD module.|
|Interrupt ControllerInterrupt control module is responsible for the interrupt manage system, for the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers. Please note, that external pins of this module are connected to appropriate pins of P3 port.|
|External Memory InterfaceContains memory access related registers, such as Data Page High (DPH), Data Page Low (DPL). It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by the user. This feature is called Program Memory Wait States, and it allows core to work with different speed program memories.|
|Internal data bus 8-bit internal data bus|
|SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.|