DRPIC166X
x4 - High Performance 8-bit RISC Microcontroller
Documentation
The DRPIC166X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip), dual ported memory. The core has been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the IP cores market.
The DRPIC166X soft core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage of this architecture, is that the instruction fetch and memory transfers can be overlapped, by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory. The DRPIC166X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions which directly operates on PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.
The DRPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode, makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC166X is delivered with fully automated testbench, complete set of tests and DoCDTM on-chip hardware debugger, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's PIC Core, has built-in support for the DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals and data and program memories. More details about DCD on Chip Debugger
Watch the DRPIC166X presentation on DCD's You Tube:
Family summary
| Design | Architecture improvement | Code space | DATA space | Program word | Number of instructions | I/O Ports | Timers | Watchdog Timer | CCP1 | USART | SLEEP Mode | DoCD TM | Size (gates) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DFPIC165X | 2 | 2k | 128 | 12 bit | 33 | 24 | 1 | + | - | - | + | - | 2700 |
| DFPIC1655X | 2 | 64k | 32 kB | 14 bit | 35 | 16 | 1 | + | - | - | + | + | 3900 |
| DFPIC166X | 2 | 64k | 32 kB | 14 bit | 35 | 32 | 3 | + | 1 | 1 | + | + | 5800 |
| DRPIC1655X | 4 | 64k | 32 kB | 14 bit | 35 | 32 | 1 | + | - | - | + | + | 4800 |
| DRPIC166X | 4 | 64k | 32 kB | 14 bit | 35 | 32 | 3 | + | 1 | 1 | + | + | 6700 |
The main features of each PIC family member have been summarized in table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and requests the core modifications.
Performance
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation |
Speed grade |
Utilized Area [TILES] |
Frequency [MHz] |
|---|---|---|---|
| FUSION | -2 | 3309 | 47 |
| ProASIC3 | -2 | 3520 | 48 |
| ProASIC3e | -2 | 3309 | 47 |
| IGLOO | STD | 3520 | 25 |
| IGLOOe | STD | 3309 | 25 |
DRPIC166X implementation results for ACTEL devices.
| Implementation |
Speed grade |
Utilized Area [LUT/PFU] |
Frequency [MHz] |
|---|---|---|---|
| EC | -5 | 1889/562 | 75 |
| ECP | -5 | 1889/562 | 75 |
| XP | -5 | 1889/562 | 67 |
DRPIC166X implementation results for LATTICE devices. The CPU features and Peripherals have been included.
| Implementation |
Speed grade |
Utilized Area [Slices] |
Frequency [MHz] |
|---|---|---|---|
| SPARTAN-IIE | -7 | 892 | 45 |
| SPARTAN-III | -5 | 900 | 63 |
| SPARTAN-IIIE | -4 | 900 | 44 |
| VIRTEX-E | -8 | 892 | 49 |
| VIRTEX-II | -6 | 902 | 90 |
| VIRTEX-II pro | -7 | 901 | 110 |
| VIRTEX-IV | -12 | 909 | 120 |
DRPIC166X implementation results for XILINX devices. The CPU features and Peripherals have been included.
| Implementation |
Speed grade |
Utilized Area [LC] |
Frequency [MHz] |
|---|---|---|---|
| APEX20KC | -7 | 1695 | 64 |
| CYCLONE | -6 | 1654 | 81 |
| CYCLONE II | -6 | 1654 | 72 |
| STRATIX | -5 | 1655 | 84 |
| STRATIX II | -3 | 1401 | 166 |
| STRATIX GX | -5 | 1655 | 84 |
DRPIC166X implementation results for ALTERA devices. The CPU features and Peripherals have been included.
CPU Features
- Software compatible with PIC16C6X industry standard
- Pipelined Harvard RISC architecture
- 4 times faster, compared to original implementation
- 35 instructions
- 14 bit wide instruction word
- Up to 32 kB of internal Data Memory
- Up to 64 K Words of Program Memory
- Configurable hardware stack
- Power saving SLEEP mode
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Technology independent HDL Source Code
- 800 MHz virtual clock frequency in a 0.35u technological process
Symbol
clk por mclr
prgdata (13:0)sleep
prgaddr (15:0)
clkwdt
portai (7:0) portbi (7:0) portci (7:0) portdi (7:0)portao (7:0)
portbo (7:0)
portco (7:0)
portdo (7:0)
trisa (7:0)
trisb (7:0)
trisc (7:0)
trisd (7:0)
ramdatai (7:0)ramdatao (7:0)
rdaddr (8:0)
ramwe
ramoe
wraddr (8:0)
t0cki ccp1iccp1o
t1cki rxdti txckirxdto
txcko
int docddataidocddatao
docdclk
prgdatao (13:0)
prgwe
Pins description
| Pin | Type | Description |
|---|---|---|
| clk | input | Global clock |
| por | input | Global reset Power On Reset |
| mclr | input | User reset |
| prgdata (13:0) | input | Data bus from program memory |
| clkwdt | input | Watchdog clock |
| portai (7:0) | input | Port A input |
| portbi (7:0) | input | Port B input |
| portci (7:0) | input | Port C input |
| portdi (7:0) | input | Port D input |
| ramdatai (7:0) | input | Data bus from int. data memory |
| t0cki | input | Timer 0 input |
| ccp1i | input | Capture channel input |
| t1cki | input | Timer 1 input |
| rxdti | input | USART - serial data input |
| txcki | input | USART Synchronous Slave mode Serial Clock input |
| int | input | External interrupt pin |
| docddatai | input | DoCDTM data input |
| sleep | output | Sleep signal |
| prgaddr (15:0) | output | Program memory address bus |
| portao (7:0) | output | Port A output |
| portbo (7:0) | output | Port B output |
| portco (7:0) | output | Port C output |
| portdo (7:0) | output | Port D output |
| trisa (7:0) | output | Data direction pins for Port A |
| trisb (7:0) | output | Data direction pins for Port B |
| trisc (7:0) | output | Data direction pins for Port C |
| trisd (7:0) | output | Data direction pins for Port D |
| ramdatao (7:0) | output | Data bus for internal data memory |
| rdaddr (8:0) | output | RAM read address bus |
| ramwe | output | Data memory write |
| ramoe | output | Data memory output enable |
| wraddr (8:0) | output | RAM write address |
| ccp1o | output | CCP1 unit - Compare/PWM channel output |
| rxdto | output | USART - Synchronous mode serial data output |
| txcko | output | USART - Asynchronous mode serial data output, Synchronous Master mode serial clock output |
| docddatao | output | DoCDTM data output |
| docdclk | output | DoCDTM clock line |
| prgdatao (13:0) | output | Program memory data bus output |
| prgwe | output | Program memory write enable |
Block Diagram
| Hardware StackIt's a configurable hardware stack. The stack space is not a part of either program or data space and the stack pointer is neither readable, nor writable. The PC is pushed onto the stack, when CALL instruction is executed or an interrupt causes a branch. The stack is popped, while RETURN, RETFIE and RETLW instruction is executed. The stack operates, as a circular buffer - this means, that after the stack has been pushed eight times, the ninth push overwrites the value, that was stored from the first push. |
| Control UnitIt performs the core synchronization and data flow control. This module manages execution of all instructions. It carries out the decode and control functions for all other blocks. It contains program counter (PC) and hardware stack. |
mclr
sleep
prgdata (13:0)
prgaddr (15:0)
| ALUArithmetic Logic Unit - performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register. |
| Watchdog TimerThe watchdog timer is a free running timer. WDT has its own clock input, separate from system clock. It means, that the WDT will run, even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP mode, the WDT timeout causes the device to wake-up and continue with normal operation. |
clkwdt
| I/O PortsThe ports block contains general purpose I/O ports and data direction registers (TRIS). The DRPIC16XXX has four 8-bit full bi-directional ports PORT A, PORT B, PORT C, PORT D. Each port's bit can be individually accessed, by bit addressable instructions. Read and write accesses to the I/O port, are performed via their corresponding SFR's PORTA, PORTB, PORTC, PORTD. The reading instruction, always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, B, C and D registers. When the bit of TRIS register is set, it means, that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance). |
portai (7:0)portbi (7:0)portci (7:0)portdi (7:0)portao (7:0)portbo (7:0)portco (7:0)portdo (7:0)trisa (7:0)trisb (7:0)trisc (7:0)trisd (7:0)
| RAM ControllerIt performs interface functions between Data Memory and DRPIC16XXX internal logic. It assures correct Data Memory addressing and data transfers. The DRPIC16XXX supports two addressing modes: direct or indirect. In Direct Addressing, the 9-bit direct address is computed from RP(1:0) bits (STATUS) and from 7 least significant bits of instruction word. Indirect addressing is possible, by using the INDF register. Any instruction using INDF register, actually accesses data pointed to by the FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF register indirectly, results in a nooperation. An effective 9-bit address is obtained, by concatenating the IRP bit (STATUS) and the 8-bit FSR register. |
ramdatai (7:0)
ramdatao (7:0)
rdaddr (8:0)
ramwe
ramoe
wraddr (8:0)
| Timer 0Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register. |
t0cki
| CCP1Compare Capture PWM unit contains a 16-bit register, which can operate as a 16-bit capture register, 16-bit compare register or as a PWM master/slave duty cycle register. |
ccp1i
ccp1o
| Timer 1Timer 1 is a 16-bit timer, consisting of two 8-bit registers (TMR1H and TMR1L). Timer 1 can operate either as a 16 bit timer (incremented in every CLK clock period) or as a Counter, incremented by rising edge on the T1CKI input pin. The Timer1 interrupt is generated by the timer overflow. |
t1cki
| Timer 2Timer 2 is a 8-bit Timer with a prescaler and postscaler. Timer2 is suitable as PWM time-base. The Timer2 module has an 8-bit period register (PR2). Timer2 is incremented, until it matches PR2 and then resets on the next increment cycle. The match output of the TMR2 register goes through a 4-bit postscaler, to generate a TMR2 interrupt. |
| USARTThe Universal Synchronous Asynchronous Receiver Transmitter module is also known as a Serial Communication Interface (SCI). The USART can be configured as a full duplex asynchronous system, that can communicate with peripheral devices or it can be configured as a half duplex synchronous system (Master or Slave). |
rxdtitxckirxdtotxcko
Interrupt ControllerInterrupt Controller module is responsible for interrupt manage system, for the external and internal interrupt sources. It contains interrupt related registers, called INTCON, PIE1, PIR1. There are seven individually maskable interrupt sources:
INTCON and PIR1 record individual interrupt requests in flag bits. A global interrupt enable (GIE) bit and Peripheral interrupts enable (PIE) bit, enable all unmasked interrupts. Each interrupt source, has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared (to disable any further interrupt), the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before re-enabling interrupts. |
int
| DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurred at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core, in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off. |
docddataidocddataodocdclkprgdatao (13:0)prgwe
clk
por
| Data bus The core internal data bus |
Units
Hardware Stack
It's a configurable hardware stack. The stack space is not a part of either program or data space and the stack pointer is neither readable, nor writable. The PC is pushed onto the stack, when CALL instruction is executed or an interrupt causes a branch. The stack is popped, while RETURN, RETFIE and RETLW instruction is executed. The stack operates, as a circular buffer - this means, that after the stack has been pushed eight times, the ninth push overwrites the value, that was stored from the first push.Control Unit
It performs the core synchronization and data flow control. This module manages execution of all instructions. It carries out the decode and control functions for all other blocks. It contains program counter (PC) and hardware stack.ALU
Arithmetic Logic Unit - performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register.Watchdog Timer
The watchdog timer is a free running timer. WDT has its own clock input, separate from system clock. It means, that the WDT will run, even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT timeout generates a Watchdog reset. If the device is in SLEEP mode, the WDT timeout causes the device to wake-up and continue with normal operation.I/O Ports
The ports block contains general purpose I/O ports and data direction registers (TRIS). The DRPIC16XXX has four 8-bit full bi-directional ports PORT A, PORT B, PORT C, PORT D. Each port's bit can be individually accessed, by bit addressable instructions. Read and write accesses to the I/O port, are performed via their corresponding SFR's PORTA, PORTB, PORTC, PORTD. The reading instruction, always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, B, C and D registers. When the bit of TRIS register is set, it means, that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance).RAM Controller
It performs interface functions between Data Memory and DRPIC16XXX internal logic. It assures correct Data Memory addressing and data transfers. The DRPIC16XXX supports two addressing modes: direct or indirect. In Direct Addressing, the 9-bit direct address is computed from RP(1:0) bits (STATUS) and from 7 least significant bits of instruction word. Indirect addressing is possible, by using the INDF register. Any instruction using INDF register, actually accesses data pointed to by the FSR (file select register). Reading INDF register indirectly, will produce 00h. Writing to the INDF register indirectly, results in a nooperation. An effective 9-bit address is obtained, by concatenating the IRP bit (STATUS) and the 8-bit FSR register.Timer 0
Main system's timer and prescaler. It operates in two modes: 8-bit timer or 8-bit counter. In the \"timer mode\", timer/prescaler registers are incremented in every instruction cycle (1 or 2 CLK periods). When the prescaler is assigned into the TIMER, prescaler ratio can be divided by 2, 4, ..., 256. In the \"counter mode\", the timer register is incremented in every falling or rising edge of T0CKI pin, depending on T0SE bit in OPTION register.CCP1
Compare Capture PWM unit contains a 16-bit register, which can operate as a 16-bit capture register, 16-bit compare register or as a PWM master/slave duty cycle register.Timer 1
Timer 1 is a 16-bit timer, consisting of two 8-bit registers (TMR1H and TMR1L). Timer 1 can operate either as a 16 bit timer (incremented in every CLK clock period) or as a Counter, incremented by rising edge on the T1CKI input pin. The Timer1 interrupt is generated by the timer overflow.Timer 2
Timer 2 is a 8-bit Timer with a prescaler and postscaler. Timer2 is suitable as PWM time-base. The Timer2 module has an 8-bit period register (PR2). Timer2 is incremented, until it matches PR2 and then resets on the next increment cycle. The match output of the TMR2 register goes through a 4-bit postscaler, to generate a TMR2 interrupt.USART
The Universal Synchronous Asynchronous Receiver Transmitter module is also known as a Serial Communication Interface (SCI). The USART can be configured as a full duplex asynchronous system, that can communicate with peripheral devices or it can be configured as a half duplex synchronous system (Master or Slave).Interrupt Controller
Interrupt Controller module is responsible for interrupt manage system, for the external and internal interrupt sources. It contains interrupt related registers, called INTCON, PIE1, PIR1. There are seven individually maskable interrupt sources:- Two external interrupts INT pin, PORTB change (pins B7:B4)
- Five internal interrups Timers 0, 1, 2, USART, CCP1
INTCON and PIR1 record individual interrupt requests in flag bits. A global interrupt enable (GIE) bit and Peripheral interrupts enable (PIE) bit, enable all unmasked interrupts. Each interrupt source, has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared (to disable any further interrupt), the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before re-enabling interrupts.